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features ? single power supply operation - low voltage range: 2.70 v - 3.60 v ? memory organization - is39lv512: 64k x 8 (512 kbit) - is39lv010: 128k x 8 (1 mbit) - IS39LV040: 512k x 8 (4 mbit) ? high performance read - 70 ns access time ? cost effective sector/block architecture - uniform 4 kbyte sectors - uniform 64 kbyte blocks (sector group - except is39lv512) ? data# polling and toggle bit features ? hardware data protection ? automatic erase and byte program - build-in automatic program verifcation - typical 16 s/byte programming time - typical 55 ms sector/block/chip erase time ? low power consumption - typical 4 ma active read current - typical 8 ma program/erase current - typical 0.1 a cmos standby current ? high product endurance - guarantee 100,000 program/erase cycles per single sector (preliminary) - minimum 20 years data retention ? industrial standard pin-out and packaging - 32-pin (8 mm x 14 mm) vsop - 32-pin plcc - optional lead-free (pb-free) package ? operation temperature range - is39lv512/010 -40 o c~+85 o c - IS39LV040 0 o c~+85 o c general description the is39lv512/010/040 are 512 kbit/1 mbit/4 mbit 3.0 volt-only flash memories. these devices are designed to use a single low voltage, range from 2.70 volt to 3.60 volt, power supply to perform read, erase and program operations. the 12.0 volt v pp power supply for program and erase operations are not required. the devices can be programmed in standard eprom programmers as well. the memory array of is39lv512 is divided into uniform 4 kbyte sectors for data or code storage. the memory arrays of is39lv010/040 are divided into uniform 4 kbyte sectors or uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). the sector or block erase feature allows users to fexibly erase a memory area as small as 4 kbyte or as large as 64 kbyte by one single erase operation without affecting the data in others. the chip erase feature allows the whole memory array to be erased in one single erase operation. the devices can be programmed on a byte-by-byte basis after performing the erase operation. the devices have a standard microprocessor interface as well as a jedec standard pin-out/command set. the program operation is executed by issuing the program command code into command register. the internal control logic automatically handles the programming voltage ramp-up and timing. the erase operation is executed by issuing the chip erase, block, or sector erase command code into command register. the internal control logic automatically handles the erase voltage ramp-up and timing. the preprogramming on the array which has not been programmed is not required before an erase operation. the devices offer data# polling and toggle bit functions, the progress or completion of program and erase operations can be detected by reading the data# polling on i/o7 or the toggle bit on i/o6. the is39lv512/010/040 are manufactured on pflash?s advanced nonvolatile cmos technology. the devices are offered in 32-pin vsop and plcc packages with 70 ns access time. 512 kbit / 1mbit / 4mbit 3.0 volt-only cmos flash memory is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 1 rev.? a 04/24/2013
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 2 rev.? a 04/24/2013 connection diagrams 3 2 - p i n p l c c 2 0 1 9 1 8 1 7 1 6 1 5 1 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 2 3 0 3 1 3 2 3 4 a 1 2 a 1 5 n c v c c w e # n c i / o 1 g n d i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 a 1 4 a 1 3 a 8 a 9 a 1 1 o e # a 1 0 c e # i / o 7 a 1 4 a 1 3 a 8 a 9 a 1 1 o e # a 1 0 c e # i / o 7 i / o 1 g n d i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 1 2 a 1 5 v c c w e # n c n c n c a 1 6 i s 3 9 l v 0 10 i s 3 9 l v 5 12 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 32-pin vso p i / o 4 o e # a 1 0 c e # i / o 7 i / o 6 i / o 5 i / o 3 g n d i / o 2 i / o 1 i / o 0 a 0 a 1 a 2 a 3 is39lv51 2 is39lv51 2 a 1 1 a 9 a 8 a 1 3 a 1 4 w e # v c c n c a 1 5 a 1 2 a 7 a 6 a 5 a 4 n c n c is39lv04 0 a 1 1 a 9 a 8 a 1 3 a 1 4 w e # v c c a 1 5 a 1 2 a 7 a 6 a 5 a 4 a 1 6 a 1 8 a 1 7 is39lv01 0 a 1 1 a 9 a 8 a 1 3 a 1 4 w e # v c c n c a 1 5 a 1 2 a 7 a 6 a 5 a 4 a 1 6 n c i / o 4 o e # a 1 0 c e # i / o 7 i / o 6 i / o 5 i / o 3 g n d i / o 2 i / o 1 i / o 0 a 0 a 1 a 2 a 3 is39lv04 0 i / o 4 o e # a 1 0 c e # i / o 7 i / o 6 i / o 5 i / o 3 g n d i / o 2 i / o 1 i / o 0 a 0 a 1 a 2 a 3 is39lv01 0 i/o 0 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 i s 3 9 l v 0 4 0 a 1 4 a 1 3 a 8 a 9 a 1 1 o e # a 1 0 c e # i/o 7 a 1 2 a 1 5 v c c w e # a 1 6 a 1 8 a 1 7 i/o 1 g n d i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i s 3 9 l v 0 10 i s 3 9 l v 5 12 i s 3 9 l v 0 4 0 i s 3 9 l v 0 10 i s 3 9 l v 5 12 i s 3 9 l v 0 4 0 i s 3 9 l v 0 10 i s 3 9 l v 5 12 i s 3 9 l v 0 4 0
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 3 rev.? a 04/24/2013 pin descriptions symbol type description a0 - a ms (1) input address inputs: for memory addresses input. addresses are internally latched on the falling edge of we# during a write cycle. ce# input chip enable: ce# goes low activates the devices internal circuitries for device operation. ce# goes high deselects the device and switches into standby mode to reduce the power consumption. we# input write enable: activate the device for write operation. we# is active low. oe# input output enable: control the devices output buffers during a read cycle. oe# is active low. i/o0 - i/o7 input/ output data inputs/outputs: input command/data during a write cycle or output data during a read cycle. the i/o pins foat to tri-state when oe# are disabled. vcc device power supply gnd ground nc no connection note: 1. a ms is the most signifcant address where a ms = a15 for is39lv512, a16 for is39lv010, and a18 for IS39LV040.
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 4 rev.? a 04/24/2013 block diagram device operation read operation the access of is39lv512/010/040 are similar to eprom. to read data, three control functions must be satisfed: ? ce# is the chip enable and should be pulled low ( v il ). ? oe# is the output enable and should be pulled low ( v il ). ? we# is the write enable and should remains high ( v ih ) . product identification the product identifcation mode can be used to identify the manufacturer and the device through hardware or software read id operation. see table 1 for pflash? manufacturer id and device id. the hardware id mode is activated by applying a 12.0 volt on a9 pin, typically used by an external programmer for selecting the right programming algorithm for the devices. refer to table 2 for bus operation modes. the software id mode is activated by a three-bus-cycle command. see table 3 for software command defnition. byte programming the programming is a four-bus-cycle operation and the data is programmed into the devices (to a logical 0) on a byte-by-byte basis. see table 3 for software command defnition. a program operation is activated by writing the three-byte command sequence followed by program address and one byte of program data into the devices. the addresses are latched on the falling edge of we# or ce# whichever occurs later, and the data are latched on the rising edge of we# or ce# whichever occurs frst. the internal control logic automatically handles the internal programming volt - ages and timing. a data 0 can not be programmed back to a 1. only erase operation can convert the 0s to 1s. the data# polling on i/o7 or toggle bit on i/o6 can be used to detect the progress or completion of a program cycle. c o m m a n d a d d r e s s l a t c h e r a s e / p r o g r a m v o l t a g e g e n e r a t o r h i g h v o l t a g e s w i t c h i / o 0 - i / o 7 i / o b u f f e r s w e # c e # o e # r e g i s t e r c e , o e l o g i c y - d e c o d e r d a t a s e n s e l a t c h a m p y - g a t i n g m e m o r y a 0 - a m s x - d e c o d e r a r r a y
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 5 rev.? a 04/24/2013 device operation (continued) chip erase the entire memory array can be erased through a chip erase operation. pre-programs the devices are not required prior to a chip erase operation. chip erase starts immediately after a six-bus-cycle chip erase command sequence. all commands will be ignored once the chip erase operation has started. the devices will return to standby mode after the completion of chip erase. sector and block erase the memory array of is39lv512/010/040 are organized into uniform 4 kbyte sectors. a sector erase operation allows to erase any individual sector without affecting the data in others. the memory array of is39lv010/040, excluding is39lv512, are also organized into uniform 64 kbyte blocks (sector group - consists of sixteen adjacent sectors). a block erase operation allows to erase any individual block. the sector or block erase operation is similar to chip erase. i/o7 data# polling the is39lv512/010/040 provide a data# polling fea - ture to indicate the progress or completion of a program and erase cycles. during a program cycle, an attempt to read the devices will result in the complement of the last loaded data on i/o7. once the program operation is completed, the true data of the last loaded data is valid on all outputs. during a sector, block, or chip erase cycle, an attempt to read the device will result a 0 on i/o7. after the erase operation is completed, an attempt to read the device will result a 1 on i/o7. i/o6 toggle bit the is39lv512/010/040 also provide a toggle bit fea - ture to detect the progress or completion of a program and erase cycles. during a program or erase cycle, an attempt to read data from the device will result a tog - gling between 1 and 0 on i/o6. when the program or erase operation is complete, i/o6 will stop toggling and valid data will be read. toggle bit may be accessed at any time during a program or erase cycle. hardware data protection hardware data protection protects the devices from un - intentional erase or program operation. it is performed in the following ways: (a) v cc sense: if v cc is below 1.8 v (typical), the write operation is inhibited. (b) write inhibit: holding any of the signal oe# low, ce# high, or we# high inhibits a write cycle. (c) noise flter: pulses of less than 5 ns (typical) on the we# or ce# input will not initiate a write operation. product identifcation data manufacturer id 9dh device id: is39lv512 1bh is39lv010 1ch IS39LV040 3eh table 1. product identifcation
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 6 rev.? a 04/24/2013 memory density block (1) block size (kbytes) sector sector size (kbytes) address range 512kbit 1 mbit 4 mbit block 0 (2) 64 sec- tor 0 4 00000h - 00fffh sec- tor 1 4 01000h - 01fffh : : : sector 15 4 0f000h - 0ffffh block 1 64 sector 16 4 10000h - 10fffh sector 17 4 11000h - 11fffh : : : sector 31 4 1f000h - 1ffffh block 2 64 20000h - 2ffffh block 3 64 30000h - 3ffffh block 4 64 40000h - 4ffffh block 5 64 50000h - 5ffffh block 6 64 60000h - 6ffffh block 7 64 70000h - 7ffffh sector/block address table notes: 1. a block is a 64 kbyte sector group which consists of sixteen adjecent sectors of 4 kbyte each. 2. block erase feature is available for is39lv010/040 only. the chip erase command should be used to erase the block 0 for the is39lv512.
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 7 rev.? a 04/24/2013 operating modes notes: 1. x can be v il , v ih or addresses. 2. a ms = most signifcant address; a ms = a15 for is39lv512, a16 for is39lv010, and a18 for IS39LV040. table 2. bus operation modes mode ce# oe# we# address i/o read v il v il v ih x (1) d out write v il v ih v il x d in standby v ih x x x high z output disable x v ih x x high z product identif- cation hardware v il v il v ih a2 - a ms (2) = x, a9 = v h (3) , a1 = v il , a0 = v il manufacturer id a2 - a ms (2) = x, a9 = v h (3) , a1 = v il , a0 = v ih device i 3. v h = 12.0 v 0.5 v.
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 8 rev.? a 04/24/2013 command sequence bus cycle 1st bus cycle addr data 2nd bus cycle addr data 3rd bus cycle addr data 4th bus cycle addr data 5th bus cylce addr data 6th bus cycle addr data read 1 addr d out chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa (1) 30h block erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba (2) 50h byte program 4 555h aah 2aah 55h 555h a0h addr d in product id entry 3 555h aah 2aah 55h 555h 90h product id exit (3) 3 555h aah 2aah 55h 555h f0h product id exit (3) 1 xxxh f0h notes: 1. sa = sector address of the sector to be erased. 2. ba = block address of the block to be erased. 3. either one of the product id exit command can be used. command definition table 3. software command defnition
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 9 rev.? a 04/24/2013 device operations flowcharts chart 1. automatic programming flowchart s t a r t l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a a 0 h t o a d d r e s s 5 5 5 h l o a d p r o g r a m d a t a t o p r o g r a m a d d r e s s i / o 7 = d a t a ? o r i / o 6 s t o p t o g g l e ? l a s t a d d r e s s ? p r o g r a m m i n g c o m p l e t e d n o n o y e s y e s a d d r e s s i n c r e m e n t
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 10 rev.? a 04/24/2013 chart 2. automatic erase flowchart device operations flowcharts (continued) s t a r t w r i t e s e c t o r , o r c h i p e r a s e c o m m a n d d a t a = f f h ? o r i / o 6 s t o p t o g g l e ? e r a s u r e c o m p l e t e d y e s n o s e c t o r e r a s e c o m m a n d l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 8 0 h t o a d d r e s s 5 5 5 h l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 3 0 h t o s a b lo ck e ra se c o mman d l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 8 0 h t o a d d r e s s 5 5 5 h l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 5 0 h t o b a l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 8 0 h t o a d d r e s s 5 5 5 h l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 1 0 h t o a d d r e s s 5 5 5 h c h i p e ra s e c o m m a n d
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 11 rev.? a 04/24/2013 chart 3. software product identifcation entry/exit flowchart device operations flowcharts (continued) notes: 1. the device will enter product identifcation mode after excuting the product id entry command. 2. under product identifcation mode, the manufacturer id and device id of devices can be read at address x0000h and x0001h where x = dont care. 3. the device returns to standby operation. l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a 9 0 h t o a d d r e s s 5 5 5 h e n t e r p r o d u c t i dent if ica t i o n m o d e (1, 2 ) l o a d d a t a a a h t o a d d r e s s 5 5 5 h l o a d d a t a 5 5 h t o a d d r e s s 2 a a h l o a d d a t a f 0 h t o a d d r e s s 5 5 5 h ex it p ro d u c t i de n t if i ca ti o n m o d e (3 ) l o a d d a t a f 0 h t o a d d r e s s x x x h ex it p ro d u c t i de n t if i ca ti o n m o d e (3 ) o r
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 12 rev.? a 04/24/2013 dc and ac operating range absolute maximum ratings (1) notes: 1. stresses under those listed in absolute maximum ratings may cause permanent dam - age to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are v cc + 0.5v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are -0.5v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0v for a period of time up to 20 ns. 3. maximum dc voltage on a9 pin is +13.0 v. during voltage transitioning period, a9 pin may overshoot to +14.0 v for a period of time up to 20 ns. minimum dc voltage on a9 pin is -0.5v. during voltage transitioning period, a9 pin may undershoot gnd to -2.0v for a period of time up to 20 ns. t e m p e r a t u r e u n d e r b i a s - 6 5 o c t o + 1 2 5 o c s t o r a g e t e m p e r a t u r e - 6 5 o c t o + 1 2 5 o c s u r f a c e m o u n t l e a d s o l d e r i n g t e m p e r a t u r e 2 4 0 o c 3 s e c o n d s i n p u t v o l t a g e w i t h r e s p e c t t o g r o u n d o n a l l p i n s e x c e p t a 9 p i n ( 2 ) - 0 . 5 v t o v c c + 0 . 5 v i n p u t v o l t a g e w i t h r e s p e c t t o g r o u n d o n a 9 p i n ( 3 ) - 0 . 5 v t o + 1 3 . 0 v a l l o u t p u t v o l t a g e w i t h r e s p e c t t o g r o u n d - 0 . 5 v t o v c c + 0 . 5 v v c c ( 2 ) - 0 . 5 v t o + 6 . 0 v temperature under bias -65c to +125c storage temperature -65c to +125c surface mount lead soldering temperature 240c 3 seconds input voltage with respect to ground on all pins except a9 pin (2) -0.5v to vcc + 0.5 v input voltage with respect to ground on a9 pin (3) -0.5v to +13.0 v all output voltage with respect to ground -0.5v to vcc + 0.5 v vcc (2) -0.5v to +6.0 v part number is39lv512/010 IS39LV040 operating temperature -40 to +85c 0 to +85c vcc power supply 2.70 v - 3.60 v 2.70 v - 3.60 v
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 13 rev.? a 04/24/2013 dc characteristics note: 1. characterized but not 100% tested. symbol parameter condition min typ max units ili input load current vin= 0 v to v cc 1 ma ilo output leakage current vi/o = 0 v to v cc 1 ma isb1 vcc standby current cmos ce#, oe# = v cc -0.3 v 0.1 5 ma isb2 vcc standby current ttl ce# = vih to vcc 0.05 3 ma icc1 vcc active read current f = 5 mhz; iout = 0 ma 4 15 ma icc2(1) vcc program/erase cur- rent 8 20 ma vil input low voltage -0.5 0.8 v vih input high voltage 0.7 vcc vcc + 0.3 v vol output low voltage iol = 2.1 ma; vcc = vccmin 0.45 v voh output high voltage ioh = -100 ma; vcc = vcc min vcc - 0.2 v
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 14 rev.? a 04/24/2013 read operations characteristics ac characteristics symbol parameter is39lv512/010/040 units trc read cycle time 70 ns tacc address to output delay 70 ns tce ce# to output delay 70 ns toe oe# to output delay 35 ns tdf ce# or oe# to output high z 0 25 ns toh output hold from oe#, ce# or address, which - ever occured frst 0 ns tvcs vcc set-up time 50 ms
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 15 rev.? a 04/24/2013 ac characteristics (continued) read operations ac waveforms output test load input test waveforms and measurement level pin capacitance ( f = 1 mhz, t = 25c ) typ max units conditions c in 4 6 pf v in = 0 v c out 8 12 pf v out = 0 v note: these parameters are characterized but not 100% tested. a d d r e s s v a l i d t r c t a c c t c e t o e t d f t o h o u t p u t v a l i d h i g h z a d d r e s s c e # o e # w e # o u t p u t v c c t v c s 3 . 0 v 0 . 0 v 1 . 5 v a c m e a s u r e m e n t l e v e l inpu t 3.3 v 1.8 k 1.3 k o u t p u t p i n 3 0 p f ( f o r 55 ns ) 1 0 0 p f ( f o r 70 ns )
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 16 rev.? a 04/24/2013 write (program/erase) operations characteristics program operations ac waveforms - we# controlled ac characteristics (continued) symbol parameter is39lv512/010/040 units min max twc write cycle time 70 ns tas address set-up time 0 ns tah address hold time 30 ns tcs ce# and we# set-up time 0 ns tch ce# and we# hold time 0 ns toeh oe# high hold time 10 ns tds data set-up time 40 ns tdh data hold time 0 ns twp write pulse width 35 ns twph write pulse width high 20 ns tbp byte programming time 40 ms tec chip or block erase time 100 ms tvcs vcc set-up time 50 ms t c h t c s t w p t w p h t b p t d h t d s t a h t a s s s e r d d a 5 5 5 5 5 5 2 a a a a 5 5 a 0 i n p u t d a t a v a l i d d a t a d a t a i n a0 - a m s o e # w e # c e # pr o g ram cycl e t w c v c c t v c s
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 17 rev.? a 04/24/2013 ac characteristics (continued) chip erase operations ac waveforms t c h t c s t w p t w p h t b p t d h t d s t a h t a s s s e r d d a 5 5 5 5 5 5 2 a a a a 5 5 a 0 i n p u t d a t a v a l i d d a t a d a t a i n a 0 - a m s o e # w e # c e # p r o g r a m c y c l e t w c v c c t v c s 0 1 5 5 5 5 a a 8 0 a a 5 5 5 2 a a 5 5 5 5 5 5 2 a a t e c t w p h t w p t a s t a h t d h t d s a o - a m s w e # c e # o e # d a t a i n t w c 5 5 5 v c c t v c s
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 18 rev.? a 04/24/2013 sector or block erase operations ac waveforms toggle bit ac waveforms ac characteristics (continued) note: toggling ce#, oe#, or both oe# and ce# will operate toggle bit. 0 3 5 5 5 5 a a 8 0 a a 5 5 5 2 a a 5 5 5 5 5 5 2 a a s e c t o r a d d r e s s t e c t w p h t w p t a s t a h t d h t d s a o - a m s w e # c e # o e # d a t a i n t w c v c c t v c s t o e h w e # c e # o e # i / o 6 t o g g l e s t o p t o g g l i n g v a l i d d a t a t o e t o g g l e d a t a t d f t o h n o te : t oggl i ng c e # , oe # , o r b o t h o e # a nd ce# wi l l o per a te t o ggl e b i t .
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 19 rev.? a 04/24/2013 data# polling ac waveforms ac characteristics (continued) note: toggling ce#, oe#, or both oe# and ce# will operate data# polling. program/erase performance parameter unit typ max remarks sector erase time ms 55 100 from writing erase command to erase completion block erase time ms 55 100 from writing erase command to erase completion chip erase time ms 55 100 from writing erase command to erase completion byte programming time ms 16 20 excludes the time of four-cycle program command execution note: 1. these parameters are characterized but not 100% tested. 2. preliminary specifcation only and will be formalized after cycling qualifcation test. t c h t c e t o e h t o e t d f t o h v a l i d d a t a i/ o 7 # w e # c e # o e # i / o 7
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 20 rev.? a 04/24/2013 package type information vsop 32-pin thin small outline package (vsop - 8 mm x 14 mm)( measure in millimeters) plcc 32-pin plastic leaded chip carrier dimensions in inches (millimeters) . 02 0 ( 0 . 5 ) b s c . 0 3 7 ( . 9 5 ) . 04 1 ( 1 . 0 5 . 006 ( . 1 6 ) . 011 ( , 2 7 ) . 020 ( 0 . 5 ) . 006 ( . 1 5 ) p in 1 i. d . . 4 8 4 ( 1 2 . 3 0 ) . 4 9 2 ( 1 2 . 5 0 ) . 5 4 3 ( 1 3 . 8 0 ) . 5 6 0 ( 1 4 . 2 0 ) . 31 5 ( 7 . 9 0 ) . 31 9 ( 8 . 1 0 ) . 0 4 7( 1 .20 ) m a x . 0 1 0 (.2 5 ) 0 5 . 0 04 ( .1 0 ) . 0 08 ( .2 0 ) . 0 2 0 (. 5 0 ) . 0 2 8 (. 7 0 ) p i n 1 i .d . . 5 8 5 ( 1 4 . 8 6 ) . 5 9 5 ( 1 5 . 1 1 ) . 5 4 7 ( 1 3 . 8 9 ) . 5 5 3 ( 1 4 . 0 5 ) . 0 5 0 r e f . . 02 6 ( . 6 6 ) . 03 2 ( . 8 1 ) . 4 4 7 ( 1 1 . 3 5 ) . 4 5 3 ( 1 1 . 5 1 ) . 4 8 5 ( 1 2 . 3 2 ) . 4 9 5 ( 1 2 . 5 1 ) 0 2 5 ( . 6 3 5 ) x 3 0 . 4 0 0 r e f . . 5 1 0 ( 1 2 . 9 5 ) . 5 3 0 ( 1 3 . 4 6 ) . 0 1 3 ( . 3 3 ) . 0 2 1 ( . 5 3 ) . 0 0 9 . 0 1 5 . 0 7 6 ( 1 . 9 3 ) . 0 9 5 ( 2 . 4 1 ) . 1 2 3 ( 3 . 1 2 ) . 1 4 0 ( 3 . 5 6 ) s e a t i n g p l a n e
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 21 rev.? a 04/24/2013 p a c ka g e t y p e l ea d - fr ee p a c ka g e e/l = lead-free t e m pe r a t u r e gr a de e = ex te nd e d g rad e (-40c to +105c) a1 = automotve grade (-40c to +85c) a2 = automotve grade (-40c to +105c) a3 = automotve grade (-40c to +125c) blank = refer to datasheet fl a s h pr o du c t fa m il y isa = 29/39 d en s i t y 025 = 256 k b 512 = 512 k b 010 = 1m b 020 = 2m b 040 = 4m b 080 = 8m b 016 = 16m b 032 = 32m b 064 = 64m b 128 = 128m b 256 = 256m b isa i n t e r f a c e v = isa x8 l = isa x8/x16 i s 39 l v 040 C 70vce temperature grade p a c k a g e t y p e p r o du c t f a m il y i ss i p re ?x v olt a g e d en s i t y i n t e r f ac e je = 48 pin tssop jt = 56 pin tssop 70jce = 32 pin plcc 70vce = 32 pin vsop (8x14mm) jh = 48 ball (bga 6x8mm) (call factory) ji = 64 ball (bga 11x13mm) (call factory) js = wlcsp (call factory) jw = kgd (call factory) g/l = 2.70-3.60v isa op e ra t n g v ol t a g e ra n g e blank = first rev. die rev. control d ie rev. control isa
is39lv512 / is39lv010 / IS39LV040 integrated silicon solution, inc. www.issi.com 22 rev.? a 04/24/2013 density frequency (mhz) order part number package 512k 100 is39lv512-70jce 32-pin plcc is39lv512-70vce 32-pin vsop 1m 100 is39lv010-70jce 32-pin plcc is39lv010-70vce 32-pin vsop 4m 100 IS39LV040-70jce 32-pin plcc IS39LV040-70vce 32-pin vsop ordering information

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